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INTEGRATED CIRCUITS
FBL2033 3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
Product specification IC23 data handbook 1999 Apr 15
Philips Semiconductors
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
FBL2033
FEATURES
* 8-bit transceivers * Latched, registered or straight through in either A to B or B to A
path
* Compatible with IEEE Futurebus+ or proprietary BTL backplanes * Each BTL driver has a dedicated Bus GND for a signal return * Controlled output ramp and multiple GND pins minimize ground
bounce
* Drives heavily loaded backplanes with equivalent load
impedances down to 10.
* High drive 100mA BTL Open Collector drivers on B-port * Allows incident wave switching in heavily loaded backplane buses * Reduced BTL voltage swing produces less noise and reduces
power consumption
* Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
* Glitch-free power up/power down operation * Low ICC current * Tight output skew * Supports live insertion * Pins for the optional JTAG boundary scan function are provided * High density packaging in plastic Quad Flatpack * 5V compatible I/O on A-port
TYPICAL 3.0 3.0 5.0 5.3 6 100 9 14 17 14 UNIT ns ns pF mA
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL COB IOL PARAMETER Propagation delay AIn to Bn Propagation delay Bn to AOn Output capacitance (B0 - Bn only) Output current (B0 - Bn only) AIn to Bn outputs Low outputs High Supply current Su ly Bn to AOn (outputs Low) Bn to AOn (outputs High)
ICC
mA
ORDERING INFORMATION
PACKAGE 52-pin Plastic Quad Flat Pack (PQFP) NOTE: Thermal mounting or forced air is recommended COMMERCIAL RANGE VCC = 3.3V10%; Tamb = -40C to +85C FBL2033BB DWG No. SOT379-1
PIN CONFIGURATION
LOGIC GND V CC BG GND BG V CC OEA LCAB SBA1 SBA0 BIAS V
AO0
AI1
AI0
52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND AO1 AI2 AO2 AI3 AO3 LOOPBACK AI4 AO4 1 2 3 4 5 6 7 8 9 39 38 37 36 BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND
8-Bit Universal Transceiver FBL2033 52-lead PQFP
B0 35 34 33 32 31 30 29 28 27 B7
AI 10 5 AO 11 5 AI 12 6 LOGIC GND 13 14 15 16 17 18 19 20 21 22 23 24 25 26 LGOIC GND BUS GND AO6 AI7 AO7 LCBA V CC OEB0 V CC SAB0 SAB1 OEB1
SG00088
1999 Apr 15
2
853-2156 21253
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
DESCRIPTION
The FBL2033 is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level side. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A, SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a register, or a D-type latch. When configured in the buffer mode, the inverse of the input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-High latch enables. Regardless of the mode, data is inverted from input to output. Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the Loopback input. When the Loopback input is High the output of the selected A-to-B logic element (not inverted) becomes the B-to-A input. The 3-State AO port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled. When either OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to the level of the pull-up voltage. New data can be entered in the flip-flop and latched modes or can be retained while the associated outputs are in 3-State (AO port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port ensure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (see the IEEE 1194.1 BTL standard). BTL features low power consumption
FBL2033
by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The "VOH" clamp reduces inductive ringing effects during a Low-to-High transition. The "VOH" clamp is always active. The other clamp, the "trapped reflection" clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition. To support live insertion, OEB0 is held Low during power on/off cycles to ensure glitch- free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 3.3V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble- shoot. As with any high power device thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature.
PIN DESCRIPTION
SYMBOL AI0 - AI7 AO0 - AO7 B0 - B7 OEB0 OEB1 OEA BUS GND LOGIC GND VCC BIAS V BG VCC BG GND SABn SBAn LCAB LCBA Loopback PIN NUMBER 50, 52, 3, 5, 8, 10, 12, 15 51, 2, 4, 6, 9, 11, 14, 16 40, 38, 36, 34, 32, 30, 28, 26 23 24 43 39, 37, 35, 33, 31, 29, 27, 25 1, 13, 17, 49 18, 22, 48 41 44 42 20, 21 45, 46 47 19 7 TYPE Input Output I/O Input Input Input GND GND Power Power Power GND Input Input Input Input Input Data inputs (TTL) 3-State outputs (TTL) Data inputs/Open Collector outputs, High current drive (BTL) Enables the B outputs when High Enables the B outputs when Low Enables the AO outputs when High Bus ground (0V) Logic ground (0V) Positive supply voltage Live insertion pre-bias pin Band Gap threshold voltage reference Band Gap threshold voltage reference ground Mode select from AI to B Mode select from B to AO A-to-B clock/latch enable (transparent latch when High) B-to-A clock/latch enable (transparent latch when High) Enables loopback function when High (from AIn to AOn) NAME AND FUNCTION
1999 Apr 15
3
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
FUNCTION TABLE
INPUTS MODE AIn L H AIn to Bn transparent latch L H AIn to Bn latch and read l h AIn to Bn register Bn outputs latched and read (preconditioned latch) Bn to AOn thru mode L H X X X Bn to AOn transparent latch X X Bn to AOn latch and read X X Bn to AOn register AOn outputs latched and read (preconditioned latch) Disable Bn outputs Disable AOn outputs X X X X X X Bn* -- -- -- -- -- -- -- -- -- L H L H l h L H X X X X OEB0 H H H H H H H H H L L L L L L L L L L X X OEB1 L L L L L L L L L H H H H H H H H H X H X OEA L L L L L L L L L H H H H H H H H H X X L LCAB X X H H L X X X X X X X X X X X X LCBA X X X X X X X X X X X H H L X X X SAB1
0
FBL2033
OUTPUTS SBA1
0
AOn Z Z Z Z Z Z Z Z Z H L H L H L H L latched data X X Z
Bn H** L H** L H** L H** L latched data input input input input input input input input X H** H** X
AIn to Bn thru mode
LL LL HX HX HX HX LH LH HX XX XX XX XX XX XX XX XX XX XX XX XX
XX XX XX XX XX XX XX XX XX LL LL HX HX HX HX LH LH HX XX XX XX
FUNCTION SELECT TABLE
MODE SELECTED Thru mode Register mode Latch mode SXX1 L L H SXX0 L H X
NOTES: H= L = h = l = X = Z = --= = = H** = Bn* =
High voltage level Low voltage level High voltage level one set-up time prior to the High-to-Low LCXX transition Low voltage level one set-up time prior to the High-to-Low LCXX transition Don't care High-impedance (OFF) state Input not externally driven Low-to-High transition High-to-Low transition Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. In Loopback mode (Loopback = High), AIn inputs are routed to the AOn outputs. The Bn inputs are blocked out.
1999 Apr 15
4
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
LOGIC DIAGRAM
OEB0 OEB1 SAB0 SAB1 LCAB 23 24 20 21 47
FBL2033
AIn
50
52, 2, 5, 8, 10, 12, 15
D En
40
Bn
D Clk 1 of 8 cells
38, 36, 34, 32, 30, 28, 26
LCBA SBA0 SBA1 OEA
19 45 46 43
D En AOn 51 D Clk 1 of 8 cells BGref Loopback 7 2, 4, 6, 9, 11, 14, 16
BGGnd
42
SG00069
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IOUT TSTG Supply voltage In ut Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state/High output state Storage temperature AO0 - AO7 B0 - B7 AI0 - AI7, OEB0, OEBn, OEAn B0 - B7 VIN t 0 PARAMETER RATING -0.5 to +4.6 -0.5 to +7.0 -0.5 to +3.5 -50 -0.5 to +7.0 64, -64 200 -65 to +150 V mA C UNIT V V
1999 Apr 15
5
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VIH VIL IIK IOH IOL COB Tamb Supply voltage High-level in ut voltage input Low-level in ut voltage input Input clamp current High-level output current Low-level out ut current output Output capacitance on B port Operating free-air temperature range 0 AO0 - AO7 AO0 - AO7 B0 - B7 6 Except B0-B7 B0 - B7 Except B0-B7 B0 - B7 3.0 2.0 1.62 1.55 0.8 1.47 -18 -12 +12 100 7 +70 COMMERCIAL LIMITS VCC = 3.3V10%; Tamb = -40 to +85C TYP 3.3 MAX 3.6
FBL2033
UNIT
V V V mA mA mA pF C
LIVE INSERTION SPECIFICATIONS
SYMBOL VBIASV IBIASV S VBn ILM IHM IBnPEAK IO OFF OL tGR Bias pin voltage Bias pin ( BIASV) input (I DC current Bus voltage during prebias Fall current during prebias Rise current during prebias Peak bus current during insertion Power up current Input glitch rejection PARAMETER Voltage difference between the Bias voltage and VCC after the PCB is plugged in. VCC = 0 V, Bias V = 3.6V VCC = 3.3V, Bias V = 3.6V B0 - B7 = 0V, Bias V = 3.3V B0 - B7 = 2V, Bias V = 1.3 to 2.5V B0 - B7 = 1V, Bias V = 3 to 3.6V VCC = 0 to 3.3V, B0 - B7 = 0 to 2.0V, Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns VCC = 0 to 3.3V, OEB0 = 0.8V VCC = 0 to 1.2V, OEB0 = 0 to 5V VCC = 3.3V 1.0 1.35 -1 10 100 100 1.62 LIMITS MIN - TYP - MAX 0.5 1.2 10 2.1 1 UNIT V mA A V A A mA A ns
1999 Apr 15
6
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. symbol IOH IO OFF parameter High level output current Power-off Power off output current B0 - B7 B0 - B7 test conditions1 VCC = MAX, VIL = MAX, VOH = 1.9V VCC = 0V, VIL = MAX, VOH = 1.9V VCC = 0V, VIL = MAX, VOH = 1.9V@85C VCC = MIN to MAX; IOH = -100A AO0 - AO73 VCC = MIN; IOH = -8mA VCC = MIN; IOH = -32mA VOL Low-level output voltage AO0 - AO73 B0 - B7 VIK Input clamp voltage Control pins II Input leakage current g Control/ AI0 - AI7 AI0 - AI7 Note 4 IIH IIL IOZH IOZL ICCH ICCL ICCZ ICCH ICCL ICCZ High-level input current B0 - B7 VCC = MIN; IOL = 16mA VCC = MIN; IOL = 32mA VCC = MIN, IOL = 4mA VCC = MIN, IOL = 100mA VCC = MIN, II = IIK = -18mA VCC = 3.6V; VI = VCC or 300mV VCC = 0V or 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 300mV VCC = MAX, VI = 1 9V MAX 1.9V VCC = MAX, VI = 3.5V, note 5 VCC = MAX, VI = 3.75V, Note 5 @ -40C Low-level Low level input current Off-state output current Off-state output current Supply current (total) Su ly Supply current Su ly Supply current (total) Supply current B0 - B7 AO0 - AO7 AO0 - AO7 BA VCC = MAX, VI = 0.75V MAX 0 75V VCC = MAX, VO =3V VCC = MAX, VO = 0.5V VCC = MAX, outputs High VCC = MAX, outputs Low VCC = MAX VCC = MAX, outputs High AB VCC = MAX, outputs Low VCC = MAX 14 17 22 14 9 14 100 100 0.5 0.75 1.0 VCC -0.2 2.4 2.0
FBL2033
limits min typ2 max 100 100 300
unit A A V V V
VOH
High level out ut High-level output voltage
0.4 0.5 1.20 -1.2 1.0 10 1 -5 100
V V V V
-0.85
A
A mA
-100 100 5 -5 31 38 55 32 18 33
A A A mA mA mA mA
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 3.3V, TA = 25C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 4. Unused pins are at VCC or GND. 5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit is active).
1999 Apr 15
7
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL PARAMETER Propagation delay, An to Bn through latch Propagation delay, An to Bn transparent latch Propagation delay, LCAB to Bn latch Propagation delay, LCAB to Bn register Propagation delay, SABX to Bn inverting Propagation delay, SABX to Bn non-inverting OEBn to Bn TEST CONDITION MIN 1.2 1.2 1.3 1.8 2.0 2.3 2.1 2.0 1.2 2.3 1.8 1.8 1.5 1.6 TYP 2.7 2.6 3.2 3.7 3.8 4.3 3.8 4.3 4.3 5.1 4.0 5.0 3.4 3.4 MAX 4.8 4.3 5.2 5.6 5.8 6.3 5.7 6.5 7.6 8.0 6.4 8.5 5.4 5.3 MIN 1.0 1.0 1.0 1.6 1.2 1.8 1.4 1.8 1.0 2.0 1.1 1.6 1.0 1.0
FBL2033
MAX 5.3 4.9 6.1 6.3 7.0 7.3 6.9 7.3 9.2 8.7 8.0 9.8 6.0 7.2
UNIT ns ns ns ns ns ns ns
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 3.3V, RL = 16.5 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation delay, An to Bn through latch Propagation delay, An to Bn transparent latch Propagation delay, LCAB to Bn latch Propagation delay, LCAB to Bn register Propagation delay, SABX to Bn inverting Propagation delay, SABX to Bn non-inverting OEBn to Bn 1.2 1.2 1.4 1.7 2.0 2.2 2.0 2.2 1.2 1.8 1.3 1.5 1.5 1.5 TYP 2.8 2.4 3.2 3.5 3.8 4.1 3.9 4.1 4.6 4.7 4.5 4.6 3.4 3.2 MAX 4.5 4.0 5.1 5.4 5.6 6.1 5.9 6.1 8.6 7.9 8.2 8.2 6.0 7.2 Tamb = -40 to +85C, VCC = 3.3V10%, RL = 16.5 MIN 1.0 1.0 1.0 1.3 1.3 1.6 1.2 1.6 1.0 1.6 1.0 1.2 1.0 1.0 MAX 5.7 4.6 6.1 5.9 6.9 7.0 7.7 7.0 10.4 8.7 10.0 9.1 6.3 7.0 ns ns ns ns ns ns ns UNIT
1999 Apr 15
8
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (B TO A)
SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPHZ tPZH tPHZ PARAMETER Propagation delay, Bn to An through mode Propagation delay, Bn to An transparent latch Propagation delay, LCAB to An latch Propagation delay, LCAB to An register Propagation delay, SABX to An inverting Propagation delay, SABX to An non-inverting Propagation delay, AIn to AOn loopback Propagation delay, LPBK to An non-inverting or inverting Propagation delay, OEA to An Propagation delay, OEA to An TEST CONDITION Tamb = +25C, VCC = 3.3V MIN 2.5 3.0 3.4 3.2 2.1 1.6 1.9 2.3 2.3 2.5 1.4 1.9 2.4 2.3 2.0 1.3 2.4 3.1 2.1 1.4 TYP 4.5 5.1 5.4 5.4 3.9 3.3 3.7 4.1 4.2 4.5 3.9 4.0 4.3 4.4 4.3 4.9 4.3 5.3 4.0 2.7 MAX 6.5 7.3 7.6 7.6 5.8 5.0 5.7 6.0 6.4 6.5 8.7 6.1 6.3 6.6 7.0 9.4 6.3 7.6 6.2 4.4
FBL2033
Tamb = -40 to +85C, VCC = 3.3V10% MIN 1.6 2.6 2.2 2.7 1.3 1.2 1.1 1.8 1.3 2.0 1.0 1.5 1.6 1.6 1.4 1.5 1.9 2.5 1.7 1.0 MAX 7.8 9.1 9.2 9.3 7.2 5.9 6.8 7.0 7.9 7.4 9.8 7.1 8.1 7.6 8.9 11.3 7.3 8.9 6.9 5.2
UNIT
ns ns ns ns ns ns ns ns ns ns
1999 Apr 15
9
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
AC SETUP REQUIREMENTS INDUSTRIAL AND COMMERCIAL
LIMITS Tamb = +25C, VCC = 3.3V
FBL2033
SYMBOL
PARAMETER
TEST CONDITION
Tamb = -40 to +85C, VCC = 3.3V10%
UNIT
CL = 50pF (A side) / CD = 30pF (B side) RL = 500 (A side) / RU = 9 (B side) MIN MIN 4.0 4.0 6.5 5.5 1.3 1.3 2.0 2.0 1.3 1.3 4.0 4.0 ns ns ns ns ns ns 3.0 3.0 6.0 5.0 1.0 1.0 1.5 1.5 1.0 1.0 3.0 3.0
ts(H) ts(L) th(H) th(L) th(H) th(L) th(H) th(L) th(H) th(L) tw(H) tw(L)
Setup time AIn to LCAB or Bn to LCBA Hold time (latch mode) AIn to LCAB Hold time (register mode) AIn to LCAB Hold time (latch mode) Bn to LCAB Hold time (register mode) Bn to LCAB Pulse width, High or Low AIn to LCAB or Bn to LCBA
AC SETUP REQUIREMENTS INDUSTRIAL AND COMMERCIAL
LIMITS Tamb = +25C, VCC = 3.3V Tamb = -40 to +85C, VCC = 3.3V10%
SYMBOL
PARAMETER
TEST CONDITION
UNIT
CL = 50pF (A side) / CD = 30pF (B side) RL = 500 (A side) / RU = 16.5 (B side) MIN MIN 4.0 4.0 6.5 5.5 1.3 1.3 2.0 2.0 1.3 1.3 4.0 4.0 ns ns ns ns ns ns 3.0 3.0 6.0 5.0 1.0 1.0 1.5 1.5 1.0 1.0 3.0 3.0
ts(H) ts(L) th(H) th(L) th(H) th(L) th(H) th(L) th(H) th(L) tw(H) tw(L)
Setup time AIn to LCAB or Bn to LCBA Hold time (latch mode) AIn to LCAB Hold time (register mode) AIn to LCAB Hold time (latch mode) Bn to LCAB Hold time (register mode) Bn to LCAB Pulse width, High or Low AIn to LCAB or Bn to LCBA
1999 Apr 15
10
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
AC WAVEFORMS
Input VM tPLH Output VM VM tPHL VM Output Input VM tPHL VM VM tPLH
FBL2033
VM
Waveform 1. Propagation Delay for Data or Output Enable to Output
Waveform 2. Propagation Delay for Data or Output Enable to Output
AIn, Bn
VM tSK(o)
AIn, Bn
AOn, Bn
VM
LCAB, LCBA
Waveform 3. Output to Output Skew
Waveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency
OEA
VM tPZH
VM tPHZ VM VOH -0.3V OV AOn OEA VM tPZL VM VM tPLZ VOL +0.3V
AOn
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
1999 Apr 15
11
IIIIIIIII IIIIIIIII
VM
ts
th
VM
ts tw(L)
th
tw(H)
VM
1/fMAX
SG00070
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V RL NEGATIVE PULSE 90% VM 10% tTHL CL RL tW VM 10%
FBL2033
90%
AMP (V)
VIN PULSE GENERATOR RT D.U.T.
VOUT
LOW V tTLH
(tf) (tr)
90% VM tW
(tr) (tf)
AMP (V)
tTLH 90% POSITIVE PULSE VM 10%
tTHL
Test Circuit for 3-State Outputs on A Port SWITCH POSITION TEST tPLZ, tPZL All other SWITCH closed open
VCC BIAS V VIN PULSE GENERATOR RT D.U.T. 2.0V (for RU = 9 ) 2.1V (for RU = 16.5 )
10%
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
Input Pulse Definitions Family FB+ A Port B Port INPUT PULSE REQUIREMENTS Amplitude 3.0V 2.0V Low V 0.0V 1.0V Rep. Rate 1MHz 1MHz tW tTLH tTHL 2.5ns 2.0ns
500ns 2.5ns 500ns 2.0ns
VOUT
RU
CD
Test Circuit for Outputs on B Port
DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00063
1999 Apr 15
12
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver
FBL2033
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
1999 Apr 15
13
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru universal transceiver
FBL2033
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 07-98 9397-750-05517
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